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Verilog Coding for Logic Synthesis

Weng Fook Lee




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 | #5499697 in Books |  Wiley-Interscience |  2003-04-17 | Original language:English | PDF # 1 |  9.41 x.83 x6.42l,1.31 | File type: PDF | 309 pages

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||1 of 1 people found the following review helpful.| Sparse Index|By Alan M. Feldstein|This is a 309-page book with a one and a half page index! I can't count how many times I have pulled out this book, looked for a particular topic in its index, and put the book back on the shelf.

Not obvious from the title, although Lee says so on the back cover, this book describes a design flow for ASIC design. That makes me wonder|From the Back Cover|A practical introduction to writing synthesizable Verilog code |Rapid change in IC chip complexity and the pressure to design more complex IC chips at a faster pace has forced design engineers to find a more efficient and productive method t

Provides a practical approach to Verilog design and problem solving.
* Bulk of the book deals with practical design problems that design engineers solve on a daily basis.
* Includes over 90 design examples.
* There are 3 full scale design examples that include specification, architectural definition, micro-architectural definition, RTL coding, testbench coding and verification.
* Book is suitable for use as a textbook in EE departments that have V...

You can specify the type of files you want, for your device.Verilog Coding for Logic Synthesis   |  Weng Fook Lee. Which are the reasons I like to read books. Great story by a great author.

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